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AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C MT5C1005 4 MEG x 1 DRAM 256K x 4 SRAM
DRAM
AVAILABLE AS MILITARY SPECIFICATONS
* SMD 5962-90622 * MIL-STD-883
4 MEG x 1 DRAM
FAST PAGE MODE
PIN ASSIGNMENT (Top View) 18-Pin DIP
D WE RAS *A10 A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 Vss Q CAS A9 A8 A7 A6 A5 A4
20-Pin ZIP
A9 Q D RAS NC A0 A2 Vcc A5 A7 1 3 5 7 9 11 13 15 17 19
FEATURES
* Industry standard x1 pinout, timing, functions and packages * High-performance, CMOS silicon-gate process * Single +5V 10% power supply * Low-power, 2.5mW standby; 300mW active, typical * All inputs, outputs and clocks are fully TTL and CMOS compatible * 1,024-cycle refresh distributed across 16ms * Refresh modes: /R?A/S-ONLY, /C/A/S-BEFORE-/R/?A/S (CBR), and HIDDEN * FAST PAGE MODE access cycle * CBR with ?W/E a HIGH (JEDEC test mode capable via WCBR)
2 4 6 8 10 12 14 16 18 20
CAS Vss WE A10* NC A1 A3 A4 A6 A8
OPTIONS
* Timing 70ns access 80ns access 100ns access 120ns access * Packages Ceramic DIP (300 mil) Ceramic DIP (400 mil) Ceramic LCC Ceramic SOJ Ceramic ZIP Ceramic Gull Wing
MARKING
-7 -8 -10 -12
20-Pin SOJ 20-Pin LCC 20-Pin Gull Wing
D WE RAS NC *A10 1 2 3 4 5 26 25 24 23 22 Vss Q CAS NC A9
CN C ECN ECJ CZ ECG
No. 101 No. 102 No. 202 No. 504 No. 400 No. 600
A0 A1 A2 A3 Vcc
9 10 11 12 13
18 17 16 15 14
A8 A7 A6 A5 A4
*Address not used for /R/A/S-ONLY REFRESH
GENERAL DESCRIPTION
The MT4C1004J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x1 configuration. During READ or WRITE cycles, each bit is uniquely addressed through the 22 address bits which are entered 11 bits (A0 -A10) at a time. /R/A/S is used to latch the first 11 bits and /C/A/S the latter 11 bits. A READ or WRITE cycle is selected with the ?W/E input. A logic HIGH on ?W/E dictates READ mode while a logic LOW on ?W/E dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the
MT4C1004J 883C REV. 11/97 DS000021
falling edge of ?W/E or /C/A/S, whichever occurs last. If ?W/E goes LOW prior to /C/?A/S going LOW, the output pin remains open (High-Z) until the next /C/A/S cycle. If ?W/E goes LOW after data reaches the output pin, Q is activated and retains the selected cell data as long as /C/A/S remains LOW (regardless of ?W/E or /R/A/S). This LATE-?W/E pulse results in a READ-WRITE cycle. FAST PAGE MODE operations allow faster data operations (READ, WRITE or READ-MODIFYWRITE) within a row-address (A0 -A10) defined page
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C MT5C1005 4 MEG x 1 DRAM 256K x 4 SRAM
boundary. The FAST PAGE MODE cycle is always initiated with a row address strobed-in by /R/A/S followed by a column address strobed-in by C/A/S. /C/A/S may be toggled-in / by holding /R/A/S LOW and strobing-in different column addresses, thus executing faster memory cycles. Returning /R/A/S HIGH terminates the FAST PAGE MODE operation. Returning /R/A/S and /C/A/S HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also,
the chip is preconditioned for the next cycle during the /R/A/ S HIGH time. Memory cell data is retained in its correct state by maintaining power and executing any /R?A/S cycle (READ, WRITE, /R?A/S-ONLY, /C/A/S-BEFORE-/R/A/S, or HIDDEN REFRESH) so that all 1,024 combinations of /R?A/S addresses (A0 -A9) are executed at least every 16ms, regardless of sequence. The /C?A/S - BEFORE-/R?A/S cycle will invoke the refresh counter for automatic /R/?A/S addressing.
FUNCTIONAL BLOCK DIAGRAM FAST PAGE MODE
WE CAS *EARLY-WRITE DETECTION CIRCUIT
DATA IN BUFFER
D
NO. 2 CLOCK GENERATOR
DATA OUT BUFFER
Q
11
ROW ADDRESS BUFFERS (11)
1 10
ROW DECODER
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
11
COLUMN ADDRESS BUFFER(11) REFRESH CONTROLLER
11
COLUMN DECODER
4096 SENSE AMPLIFIERS I/O GATING 4096
REFRESH COUNTER 10
1024
MEMORY ARRAY
RAS
NO. 1 CLOCK GENERATOR
Vcc Vss
*NOTE: WE LOW prior to CAS LOW, EW detection circuit output is a HIGH (EARLY-WRITE) CAS LOW prior to WE LOW, EW detection circuit output is a LOW (LATE-WRITE)
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C MT5C1005 4 MEG x 1 DRAM 256K x 4 SRAM
TRUTH TABLE
ADDRESSES FUNCTION Standby READ EARLY-WRITE READ-WRITE FAST-PAGE-MODE 1st Cycle READ EARLY-WRITE READ-WRITE HIDDEN REFRESH 2nd Cycle 2nd Cycle 2nd Cycle READ WRITE FAST-PAGE-MODE 1st Cycle FAST-PAGE-MODE 1st Cycle /R/A/S-ONLY REFRESH ?R/A/S H L L L L L L L L L L L>H>L L>H>L H>L ?C/A/S H>X L L L H>L H>L H>L H>L H>L H>L H L L L ?W/E X H L H>L H H L L H>L H>L X H L H
tR tC
DATA D (Data In) Don't Care Don't Care Data In Data In Don't Care Don't Care Data In Data In Data In Data In Don't Care Don't Care Data In Don't Care Q (Data Out) High-Z Data Out High-Z Data Out Data Out Data Out High-Z High-Z Data Out Data Out High-Z Data Out High-Z High-Z
X ROW ROW ROW ROW n/a ROW n/a ROW n/a ROW ROW ROW X
X COL COL COL COL COL COL COL COL COL n/a COL COL X
/C/A/S-BEFORE-/R/A/S REFRESH
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C MT5C1005 4 MEG x 1 DRAM 256K x 4 SRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin Relative to VSS ............... -1.0V to +7.0V Power Dissipation ............................................................. 1W Short Circuit Output Current ..................................... 50mA Lead Temperature (Soldering 5 Seconds)................. 270C Storage Temperature ................................... -65C to +150C
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (-55C TA 125C; VCC = 5V 10%) PARAMETER/CONDITION Supply Voltage Input High (Logic 1) Voltage, All Inputs Input Low (Logic 0) Voltage, All Inputs INPUT LEAKAGE CURRENT Any Input 0V VIN 5.5V (All other pins not under test = 0V) OUTPUT LEVELS Output High Voltage (IOUT = -5mA) Output Low Voltage (IOUT = 4.2mA) VCC=5.5V SYMBOL VCC VIH VIL II IOZ VOH VOL MIN 4.5 2.4 -.5 -5 -5 2.4 0.4 MAX 5.5 VCC+.5 0.8 5 5 UNITS V V V A A V V NOTES
OUTPUT LEAKAGE CURRENT (Q is Disabled, 0V VOUT 5.5V) VCC=5.5V
MAX PARAMETER/CONDITION STANDBY CURRENT (TTL) (/R/A/S = /C/A/S = VIH) STANDBY CURRENT (CMOS) (/R/A/S = /C/A/S = VCC -0.2V; all other inputs = VCC -0.2V) OPERATING CURRENT: Random READ/WRITE Average Power-Supply Current (/R/A/S, /C/A/S, Address Cycling: tRC = tRC (MIN)) OPERATING CURRENT: FAST PAGE MODE Average Power-Supply Current (/R/A/S = VIL, /C/A/S, Address Cycling: tPC = tPC (MIN)) REFRESH CURRENT: /R/A/S-ONLY Average Power-Supply Current (/R/A/S Cycling, /C/A/S = VIH: tRC = tRC (MIN)) REFRESH CURRENT: /C/A/S-BEFORE-/R/A/S Average Power-Supply Current (/R/A/S, /C/A/S, Address Cycling: tRC = tRC (MIN)) SYMBOL ICC1 ICC2 -7 4 2 -8 4 2 -10 4 2 -12 4 2 UNITS NOTES mA mA
ICC3
85
75
65
65
mA
3, 4
ICC4
60
50
45
40
mA
3, 4
ICC5
85
75
65
65
mA
3
ICC6
85
75
65
65
mA
3, 5
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C MT5C1005 4 MEG x 1 DRAM 256K x 4 SRAM
CAPACITANCE
PARAMETER Input Capacitance: A0-A10, D Input Capacitance: /R/A/S, /C/A/S, ?W/E Output Capacitance: Q SYMBOL CI1 CI2 CO MIN MAX 7 7 8 UNITS pF pF pF NOTES 2 2 2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (-55C TC 125; VCC = 5V 10%)
AC CHARACTERISTICS PARAMETER Random READ or WRITE cycle time READ-WRITE cycle time FAST- PAGE-MODE READ or WRITE cycle time FAST- PAGE-MODE READ-WRITE cycle time -7 SYM tRC tRWC tPC
tPRWC
-8 MAX MIN 150 175 45 70 MAX MIN 180 210 55 85 80 20 40 40 10,000 100,000
-10 MAX MIN 220 255 70 140 90 25 45 45 10,000 100,000
-12 MAX UNITS NOTES ns ns ns ns 120 30 60 60 100,000 100,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 14 15
MIN 130 155 40 65
tRAC Access time from /R/A/S tCAC Access time from /C/A/S tAA Access time from column address tCPA Access time from /C/A/S precharge tRAS /R/A/S pulse width tRASP /R/A/S pulse width (FAST PAGE MODE) tRSH /R/A/S hold time tRP /R/A/S precharge time tCAS /C/A/S pulse width tCSH /C/A/S hold time tCPN /C/A/S precharge time /C/A/S precharge time (FAST PAGE MODE) tCP tRCD /R/A/S to /C/A/S delay time tCRP /C/A/S to /R/A/S precharge time tASR Row address setup time tRAH Row address hold time tRAD /R/A/S to column address delay time
70 70 20 50 20 70 10 10 20 5 0 10 15 0 15 50 35 0 0 0 0 0 0
70 20 35 35 10,000 100,000
10,000
50
35
80 80 20 60 20 80 10 10 20 5 0 10 15 0 20 60 40 0 0 0 0 0 0
10,000
60
40
100 100 25 70 25 100 12 12 25 5 0 15 20 0 25 70 50 0 0 0 0 0 0
10,000
75
50
120 120 30 90 30 120 15 15 25 10 0 15 20 0 25 85 60 0 0 0 0 0 0
10,000
16 17
90
60
18
Column address setup time Column address hold time Column address hold time (referenced to /R/A/S) Column address to /R/A/S lead time Read command setup time Read command hold time (referenced to /C/A/S) Read command hold time (referenced to /R/A/S) /C/A/S to output in Low-Z Output buffer turn-off delay ?W/E command setup time
MT4C1004J 883C REV. 11/97 DS000021
tASC tCAH tAR tRAL tRCS tRCH tRRH tCLZ tOFF tWCS
19 19
20
20
20
20
20 21
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C MT5C1005 4 MEG x 1 DRAM 256K x 4 SRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (-55C TC 125; VCC = 5V 10%)
AC CHARACTERISTICS PARAMETER Write command hold time Write command hold time (referenced to /R/A/S) Write command pulse width Write command to /R/A/S lead time Write command to /C/A/S lead time Data-in setup time Data-in hold time Data-in hold time (referenced to /R/A/S) /R/A/S to ?W/E delay time Column address to ?W/E delay time /C/A/S to ?W/E delay time Transition time (rise or fall) Refresh period (1,024 cycles) /R/A/S to /C/A/S precharge time /C/A/S setup time (/C/A/S-BEFORE-/R/A/S REFRESH) /C/A/S hold time (/C/A/S-BEFORE-/R/A/S REFRESH) ?/W/E hold time (/C/A/S-BEFORE-/R/A/S REFRESH) ?/W/E setup time (/C/A/S-BEFORE-/R/A/S REFRESH) ?/W/E hold time (WCBR test cycle) ?/W/E setup time (WCBR test cycle) -7 SYM tWCH tWCR
tWP tRWL tCWL tDS tDH tDHR tRWD tAWD tCWD tT tREF tRPC tCSR tCHR tWRH tWRP tWTH tWTS
-8 MAX MIN 15 60 15 20 20 0 15 60 80 40 20 3 0 10 15 10 10 10 10 MAX MIN 20 70 20 25 25 0 18 70 100 50 25 3 0 10 20 10 10 10 10
-10 MAX MIN 25 85 25 30 30 0 25 90 120 60 30 3 0 10 25 10 10 10 10
-12 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns NOTES
MIN 15 50 15 20 20 0 12 50 70 35 20 3 0 10 10 10 10 10 10
22 22
21 21 21
50 16
50 16
50 16
50 16
5 5 24, 25 24, 25 24, 25 24, 25
MT4C1004J 883C REV. 11/97 DS000021
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C MT5C1005 4 MEG x 1 DRAM 256K x 4 SRAM
NOTES
1. All voltages referenced to VSS. 2. This parameter is sampled, not 100% tested. Capacitance is measured with Vcc = 5V, f = 1 MHz at less than 50mVrms, TA = 25C 3C, Vbias = 2.4V applied to each input and output individually with remaining inputs and outputs open. 3. ICC is dependent on cycle rates. 4. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the output open. 5. Enables on-chip refresh and address counters. 6. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-55C TA 125C) is assured. 7. An initial pause of 100s is required after power-up followed by eight /R?A/S refresh cycles (/R/A/S-ONLY or CBR with ?/W/E HIGH) before proper device operation is assured. The eight /R/A/S cycle wake-up should be repeated any time the 16ms refresh requirement is exceeded. 8. AC characteristics assume tT = 5ns. 9. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 10. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 11. If /C/A/S = VIH, data output is High-Z. 12. If /C/A/S = VIL, data output may contain data from the last valid READ cycle. 13. Measured with a load equivalent to 2 TTL gates and 100pF. 14. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 15. Assumes that tRCD tRCD (MAX). 16. If /C/A/S is LOW at the falling edge of /R/A/S, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, /C/A/S must be pulsed HIGH for tCPN. 17. Operation within the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, then access time is controlled exclusively by tCAC. 18. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, then access time is controlled exclusively by tAA. 19. Either tRCH or tRRH must be satisfied for a READ cycle. 20. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 21. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE, READ-WRITE and READ-MODIFY-WRITE cycles only. If tWCS tWCS (MIN), the cycle is an EARLY-WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tRWD tRWD (MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions are met, the cycle is a LATE-WRITE and the state of Q is indeterminate (at access time and until /C/A/S goes back to VIH). 22. These parameters are referenced to /C/A/S leading edge in EARLY-WRITE cycles and ?W/E leading edge in LATE-WRITE or READ-WRITE cycles. 23. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case ?W/E = LOW. 24. tWTS and tWTH are set up and hold specifications for the ?W/E pin being held LOW to enable the JEDEC test mode (with CBR timing constraints). These two parameters are the inverts of tWRP and tWRH in the CBR REFRESH cycle. 25. JEDEC test mode only.
MT4C1004J 883C REV. 11/97 DS000021
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C MT5C1005 4 MEG x 1 DRAM 256K x 4 SRAM
READ CYCLE
tRC tRAS V IH V IL tCSH tRSH tCAS tRRH tRP
RAS
CAS
ADDR
WE
,, , ,,,, ,, ,, , , , ,, , ,, , , ,, ,
tCRP tRCD V IH V IL tAR tRAD tRAH tRAL tASR tASC tCAH V IH V IL ROW COLUMN ROW tRCS tRCH V IH V IL tAA tRAC tCAC tCLZ Q V OH V OL OPEN
,,
tOFF
VALID DATA
OPEN
EARLY-WRITE CYCLE
tRC tRAS V IH V IL tCSH tRSH tCAS tRP
RAS
CAS
ADDR
WE
MT4C1004J 883C REV. 11/97 DS000021
, , , ,,,,,, , , ,, ,,,, , , ,,,,,, ,, , ,, , ,, , , ,,,,,, ,,, , ,,, ,, ,
tCRP tRCD V IH V IL tAR tRAD tRAH tRAL tASR tASC tCAH V IH V IL ROW COLUMN ROW tCWL tRWL tWCR tWCH tWP tWCS V IH V IL tDHR tDH tDS D V IH V IL VALID DATA Q V OH V OL OPEN
DON'T CARE UNDEFINED
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C MT5C1005 4 MEG x 1 DRAM 256K x 4 SRAM
READ-WRITE CYCLE (LATE-WRITE and READ-MODIFY-WRITE CYCLES)
tRWC tRAS V IH V IL tCSH tRSH tRP
RAS
CAS
ADDR
,,, ,,, ,,,,,,, ,, , , , ,, , , , , ,, , ,, ,, ,, ,, ,,,, ,,,,,,
V IH V IL tAR tASR tRAD tRAH tRAL tASC tCAH V IH V IL ROW COLUMN ROW tRWD tCWL tRWL tWP tRCS tCWD tAWD WE V IH V IL tDS tDH D V IH V IL Q V OH V OL OPEN
tCRP
tRCD
tCAS
FAST-PAGE-MODE READ CYCLE
tRASP V IH V IL tCSH tCRP tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCPN tRP
,, ,,
tAA tRAC tCAC t CLZ
tCAH COLUMN tRCS tRCH
VALID DATA
tOFF
VALID DATA
OPEN
RAS
CAS
ADDR
WE
Q
MT4C1004J 883C REV. 11/97 DS000021
, ,, ,,, ,,, ,,,,, ,, ,, , , , ,, , , , ,, , , , ,V , ,, , , , , , ,,, ,
V IH V IL tAR tRAD tRAH tRAL tASR tASC tCAH tASC tASC tCAH V IH V IL ROW COLUMN COLUMN ROW tRCS tRCS tRCH tRCH tRRH V IH V IL tAA tAA tAA tRAC tCAC tCPA tCPA tOFF tCAC tOFF tCAC tOFF tCLZ tCLZ tCLZ V OH V OL OPEN ALID DATA VALID DATA VALID DATA OPEN
DON'T CARE UNDEFINED
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C MT5C1005 4 MEG x 1 DRAM 256K x 4 SRAM
FAST-PAGE-MODE EARLY-WRITE CYCLE
tRASP V IH V IL tRP
RAS
CAS
ADDR
WE
D
Q
,, , , ,, ,, ,, , , ,,,, ,,, ,,, ,, , , , ,,,, ,,, ,,
tCRP tRCD tCAS tCP tCAS tCP V IH V IL tAR tRAD tASR tRAH tASC tCAH tASC tCAH V IH V IL ROW COLUMN COLUMN tCWL tWP tCWL tWP tWCS tWCH tWCS tWCH V IH V IL tWCR tDHR tDH tDS tDS tDH V IH V IL V IH V IL VALID DATA VALID DATA OPEN
tCSH
tPC
tRSH
tASC
COLUMN
tWCS
tDS
VALID DATA
,, ,, ,,,, ,, ,, ,,
tRAL tCAH ROW tCWL tWP tWCH tRWL tDH
tCAS
tCPN
FAST-PAGE-MODE READ-WRITE CYCLE (LATE-WRITE and READ-MODIFY-WRITE CYCLES)
tRASP tRP
RAS
V IH V IL tCSH tCRP tRCD tCAS
ADDR
*tPC = LATE-WRITE Cycle tPRWC = FAST READ-MODIFY-WRITE Cycle
MT4C1004J 883C REV. 11/97 DS000021
,, ,, ,,, ,, ,,,, , , ,, , , , , , ,,, , , , , ,, ,,, , ,, ,, , , ,,,, ,, , , ,, , , ,,,, ,,
tCP tCAS tCP tCAS tCPN CAS V IH V IL tAR tRAD tRAH tRAL tASR tASC tCAH tASC tCAH tASC tCAH V IH V IL ROW COLUMN COLUMN COLUMN ROW tRWD tRCS tAWD tRWL tCWL tWP tCWL tWP tCWL tWP tAWD tAWD tCWD tCWD tCWD WE V IH V IL tDS tDH tDS tDH tDS tDH D V IH V IL VALID DATA tAA VALID DATA tAA VALID DATA tAA tCPA tCPA tRAC tCAC tOFF tCAC tOFF tCAC tOFF tCLZ tCLZ tCLZ Q V OH V OL OPEN VALID DATA VALID DATA VALID DATA OPEN
* tPC
tPRWC
tRSH
DON'T CARE UNDEFINED
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AUSTIN SEMICONDUCTOR, INC.
/R/A/S-ONLY REFRESH CYCLE (ADDR = A0-A9; A10 and ?W/E = DON'T CARE)
tRC
MT4C1004J 883C MT5C1005 4 MEG x 1 DRAM 256K x 4 SRAM
RAS
CAS
ADDR
,,
V IH V IL V IH V IL V Q V OH OL
V IH V IL
tCRP
tASR
tRAH
ROW
,,,,,, ,,, , ,
tRPC OPEN
tRAS
tRP
ROW
/C/A/S-BEFORE-//R/A/S REFRESH CYCLE (A0-A10 = DON'T CARE)
tRP RAS V IH V IL tRPC tRPC tRAS tRP tRAS
CAS
WE
,,,,,,,,,,,,,,,,, ,, ,
tCPN tCSR tCHR tCSR tCHR V IH V IL Q OPEN tWRP tWRH tWRP tWRH V IH V IL
HIDDEN REFRESH CYCLE 23 (?W/E = HIGH)
(READ) tRAS tRP
(REFRESH) tRAS
RAS
CAS
ADDR
Q
V OH V OL
, ,,,,,,,,,,,,, , ,, , , , , , , ,
tCRP tRCD tRSH tCHR V IH V IL tAR tRAD tASR tRAH tASC tRAL tCAH V IH V IL ROW COLUMN tAA tRAC tCAC tCLZ tOFF OPEN VALID DATA OPEN
V IH V IL
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
,
DON'T CARE UNDEFINED
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C MT5C1005 4 MEG x 1 DRAM 256K x 4 SRAM
4 MEG POWER-UP AND REFRESH CONSTRAINTS
The EIA/JEDEC 4 Meg DRAM introduces two potential incompatibilities compared to the previous generation 1 Meg DRAM. The incompatibilities involve refresh and power-up. Understanding these incompatibilities and providing for them will offer the designer and system user greater compatibility between the 1 Meg and 4 Meg.
POWER-UP
The 4 Meg JEDEC test mode constraint may introduce another problem. The 1 Meg POWER-UP cycle requires a 100s delay followed by any eight ?R?A/S cycles. The 4 Meg POWER-UP is more restrictive in that eight ?R?A/S-ONLY or CBR REFRESH (?W/E held HIGH) cycles must be used. The restriction is needed since the 4 Meg may power-up in the JEDEC specified test mode and must exit out of the test mode. The only way to exit the 4 Meg JEDEC test mode is with either a ?R?A/S-ONLY or a CBR REFRESH cycle (?W/E held HIGH).
REFRESH
The most commonly used refresh mode of the 1 Meg is the CBR (?C?A/S-BEFORE-?R?A/S) REFRESH cycle. The CBR for the 1 Meg specifies the ?W/E pin as a "don't care." The 4 Meg, on the other hand, specifies the CBR REFRESH mode with the ?W/E pin held at a voltage HIGH level. A CBR cycle with ?W/E LOW will put the 4 Meg into the JEDEC specified test mode (WCBR).
SUMMARY
1. The 1 Meg CBR REFRESH allows the ?W/E pin to be "don't care" while the 4 Meg CBR requires ?W/E to be HIGH. 2. The eight ?R?A/S wake-up cycles on the 1 Meg may be any valid ?R?A/S cycle while the 4 Meg may only use ?R?A/SONLY or CBR REFRESH cycles (?W/E held HIGH).
tRP RAS V IH V IL
tRAS
tRP
tRAS
CAS Q
V IH V IL V OH V OL
WCBR TEST MODE: WE 4 MEG DRAM
CBR REFRESH: WE
1 MEG DRAM
CBR REFRESH: WE
,,, ,,,,,, ,, ,, ,,,,,,,,,, ,,,,, ,, , ,, , ,, , ,
tCPN tCSR tCHR tRPC tCSR tCHR OPEN tWTS tWTH tWTS tWTH V IH V IL tWRP tWRH tWRP tWRH V IH V IL V IH V IL
tRPC
DON'T CARE
COMPARISON OF 4 MEG TEST MODE AND WCBR TO 1 MEG CBR
MT4C1004J 883C REV. 11/97 DS000021
2-34
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C MT5C1005 4 MEG x 1 DRAM 256K x 4 SRAM
ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS (Method 5004) FINAL ELECTRICAL TEST PARAMETERS (Method 5004) GROUP A TEST REQUIREMENTS (Method 5005) GROUP C AND D END-POINT ELECTRICAL PARAMETERS (Method 5005) SUBGROUPS (per Method 5005, Table I) 2, 8A, 10 1*, 2, 3, 7*, 8, 9, 10, 11 1, 2, 3, 4**, 7, 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11
* PDA applies to subgroups 1 and 7. ** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input or output capacitance.
MT4C1004J 883C REV. 11/97 DS000021
2-35
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C MT5C1005 4 MEG x 1 DRAM 256K x 4 SRAM
MT4C1004J 883C REV. 11/97 DS000021
2-36
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.

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